Hybrid Staff Hardware Security I/O Engineer

at Factorial

• Job title: Staff Hardware Security I/O Engineer
• Job type: Full Time
• Experience level: Lead
• Salary: Not specified
• Degree requirement: Bachelor's Degree
• Location requirements: Hybrid, Barcelona, Spain

About the role

• Hardware Security I/O Engineer responsible for designing advanced hardware IPs and integrating security features in SoCs. Collaborating with cross-functional teams to deliver reliable high-performance systems.

Responsibilities

• Take ownership of designing, developing, and integrating advanced hardware IPs along with secure SoC features to deliver high-performance, reliable systems
• Drive the design, development, and integration of advanced I/O solutions and complex IPs, including the integration of third-party IPs
• Lead the implementation of security features across the SoC to ensure hardware integrity, confidentiality, and robustness
• Lead the design of some hardware subsystems, including processing units, interconnects, memory, accelerators, and analog components
• Contribute and participate in all aspects of IP development – including architecture definition, and integration to ensure high compatibility, performance, and security in complex SoC ecosystems
• Collaborate closely with several teams, such as system, product, architecture, software, digital design, and verification team, to ensure the cross-functional and design convergence
• Evaluate and integrate hard and soft Security and I/O IPs
• Develop and apply security models, threat analysis, and Trusted Computing Base concepts, such as Root of Trust and secure boot
• Stay updated on emerging technologies, industry standards, and trends to continuously innovate I/O and security solutions
• Manage complex dependencies across SoC project milestones, driving issue resolution with cross-team collaboration
• Define and advance scalable methodologies, tools, and IP building blocks for efficient SoC development
• Facilitate clear communication, knowledge sharing, and collaboration throughout the full product development lifecycle with a security focus

Requirements

• Bachelor’s, Master’s or PhD in Electrical Engineering, Computer Engineering or related field
• 10+ years of solid experience in IP/SoC architecture and design and implementation for ASIC or FPGA
• In-depth understanding of the Processor Microcontroller Subsystem (PuC SS), including secure boot processes and power management techniques for chiplets (RISC-V core)
• Expertise in High-Speed I/O subsystems, managing interfaces such as UCIe and PCIe for high-bandwidth peripheral connectivity (Ethernet, PCIe, CXL, UCIe, LPDDR)
• Proficiency in Low-Speed I/O subsystem design and integration, managing slower peripheral interfaces (APB Peripherals, I2C, I3C, UART)
• Strong knowledge of Data Management principles, including data organization, buffering, and ensuring data integrity within SoC component (DMA)
• Experience with Network-on-Chip (NoC) architectures, enabling efficient internal communication within SoC components (AMBA, AXI, CHI)
• Comprehensive understanding of hardware Security Features, including implementation of cryptographic modules, isolation, attestation, and trusted computing bases (AES, RSA, PUF, Random number generation, and related security technologies)
• Capability to design and integrate Monitoring & Sensor systems to track chiplet health and operational status
• Ability to collaborate across design, verification, firmware, and system teams to ensure robust subsystem integration and security
• Knowledge of industry standards relevant to I/O and hardware security protocols.

Benefits

• Join an innovative team and experience company growth
• We believe in investing in our employees
• Providing opportunities to grow and develop careers
• Enjoy a hybrid work environment
• Flexible schedule
• Competitive compensation package