Hybrid Senior Physical Design Engineer

at Factorial

• Job title: Senior Physical Design Engineer
• Job type: Full Time
• Experience level: Senior
• Salary: Not specified
• Degree requirement: Bachelor's Degree
• Tech skills: Perl, Python
• Location requirements: Hybrid, Roma, Italy

About the role

• Physical Design Senior Engineer overseeing implementation of complex digital blocks at an innovative microelectronics company. Ensuring design intent preservation during the physical implementation phase with focus on advanced methodologies.

Responsibilities

• Advanced Physical Implementation & Constraint Ownership
• Full-Flow Execution: Take technical ownership of the RTL-to-GDSII implementation, including Floorplanning, Place and Route (P&R), and Clock Tree Synthesis (CTS).
• Execution Strategy: Drive a "constraint-driven" approach to minimize iterations and ensure optimal physical results.
• Bottleneck Resolution: Analyze functional contexts to identify and resolve routing congestion and timing bottlenecks proactively.
• Constraint Maintenance: Hands-on management of SDC constraints at every stage; responsible for cleaning, regenerating, and validating timing constraints to ensure they reflect silicon reality (e.g., Multi-Cycle Paths, False Paths).
• Timing Closure & ECO Implementation
• Sign-off Focus: Deliver complex timing closure for designs with multiple clock domains and asynchronous interfaces using DMSA and OCV/AOCV/POCV techniques.
• Advanced ECO Execution: Implement Engineering Change Orders (ECO) at the gate level and propose physical-level adjustments when required to meet timing or power targets.
• Design Integrity: Perform and validate Signal Integrity (SI) and Power Integrity (IR-Drop/EM) analyses to ensure robust sign-off.

Requirements

• Experience: 10+ years of professional experience in Semiconductor Physical Design and Digital Implementation.
• SDC Expertise: Expert knowledge of SDC format with the ability to write, debug, and manage complex constraints for Multi-Mode Multi-Corner (MMMC) designs.
• Timing & STA: Solid hands-on experience with STA tools (PrimeTime or Tempus) and managing violations in advanced technology nodes or critical environments (e.g., Automotive).
• CDC Knowledge: Proficiency in Clock Domain Crossing (CDC) analysis and verification.
• Automation Skills: Excellent scripting capabilities (Tcl, Python, or Perl) for flow automation and report analysis.

Benefits

• Join a highly innovative microelectronics company working at the forefront of RISC-V and advanced SoC technologies.
• Opportunity to play a key technical leadership role bridging industry and public research.
• Collaboration with top-tier research institutions and industrial partners across Europe.
• Flexible working conditions and hybrid work environment.
• Competitive remuneration aligned with seniority and expertise.
• Position based in Rome.