Junior DFT Engineer involved in silicon design execution and DFT measure verification. Collaborate with cross-function teams for effective DFT solutions in Barcelona.
Responsibilities
Work on design execution of silicon design
Work on SoC DFT architecture and DFM concept
Work on implementation and verification of DFT measures to meet product specifications and production requirements
Work closely with cross-function teams (design, production test and qualification) to meet test requirements with effective DFT solutions
Contribute to target coverage requirements for logic, memories, IO and mixed-signal IPs
Generate test patterns and support post-silicon ATE and QnR.
Requirements
Bachelor's degree in Electrical or Electronic Engineering
Basic understanding of digital IC design principles
Familiarity with RTL design concepts
Exposure to DFT concepts, including scan, test controller, and MBIST
Knowledge of HDL (Verilog or VHDL) and basic synthesis concepts
Ability to learn and use EDA tools, such as VCS, TestMax DFT/ATPG/Advisor
Strong analytical and problem-solving skills.
Understanding of basic network concepts: Familiarity with networking principles, such as protocols (TCP/IP, Ethernet), topologies, and routing.
Exposure to RISC-V architecture.
Knowledge of digital design fundamentals: Familiarity with digital logic gates, combinational and sequential circuits, and basic design methodologies.
Ability to learn and adapt to new tools.
Knowledge of scripting languages: Perl, Python.
Benefits
Join an innovative team and experience company growth.
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