Hybrid Senior Mask Layout Engineer

at IonQ

• Job title: Senior Mask Layout Engineer
• Job type: Full Time
• Experience level: Senior
• Salary: $110,336 - $144,459 per year
• Degree requirement: Bachelor's Degree
• Tech skills: Python, Shell Scripting
• Location requirements: Hybrid, United States

About the role

• Senior Mask Layout Engineer at IonQ developing layouts for quantum computers. Collaborating with cross-functional teams and conducting physical verification checks in a remote-friendly environment.

Responsibilities

• Conduct Python-based layout for full-reticle tapeouts with commercial foundries
• Develop and maintain internal component PCell and automated circuit layout libraries
• Interface with designers, test engineers, packaging engineers, and foundry team to define layout rules and component designs
• Implement physical verification checks of layouts, including DRC and LVS
• Develop detailed documentation of tapeouts and lead layout reviews with other team members
• Work with cross-functional teams to understand circuit requirements and make recommendations to improve design, layout, and test workflows

Requirements

• Bachelor’s degree in Photonics, Physics, Electrical Engineering, or related field, or equivalent practical experience
• Knowledge of semiconductor manufacturing processes and techniques
• Excellent programming and software skills, including development in an IDE, proficiency with version control software, shell scripting, and code documentation
• 2+ years of experience with Python-based mask layout software packages such as Luceda IPKISS, GDSFactory, or Klayout
• M.S. or Ph.D. in Photonics, Physics, Electrical Engineering, or related field (preferred)
• 5+ years experience in generating layout files for complex semiconductor flows with custom elements, such as MEMS, integrated photonics, or superconducting circuits (preferred)
• Past ownership of full-reticle tapeouts with commercial foundries (preferred)
• Experience with commercial simulation, verification, and layout environments such as Synopsys, Cadence, and Ansys (preferred)
• Familiarity with photonic and/or analog electronic device principles including design, test, and fabrication (preferred)
• Proficiency in physical verification including DRC, LVS, and ERC (preferred)
• Experience with semiconductor and/or photonic workflows for tapeout with commercial foundries (preferred)
• Excellent verbal and written communication skills (preferred)
• A meticulous attention to detail and excellent track record of documenting requirements, implementation plan, and tracking progress (preferred)
• Ability to work independently, prioritizing tasks and managing time effectively in a deadline-oriented environment (preferred)

Benefits

• Comprehensive medical, dental, and vision plans
• Matching 401K
• Unlimited PTO and paid holidays
• Parental/adoption leave
• Legal insurance
• Home internet stipend
• Pet insurance