Own and drive the SoC-level verification strategy, planning, and execution from testbench architecture to coverage closure.
Lead and mentor a team of verification engineers to deliver high-quality verification on schedule.
Manage SoC verification deliverables including test plan, environment, coverage metrics, and signoff criteria.
Experience in multiple disciplines such as board/system manufacturing and test (HW and SW), ASIC/SOC and IP verification.
Develop test plans and coverage models for system-level features, including interconnect fabrics (IOSF) and SoC-Level Verification.
Drive integration and verification of multiple IPs - including CXL, PCIe, DDR, Ethernet, FEC, Smart NIC, PCIe Switch, Audio DSP, and custom accelerators - into the SoC environment.
Lead debug and issue triage across SoC simulations, emulations, and pre-silicon bring-up environments.
Lead clock and reset verification at block level and SOC for consumer electronic products.
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