Onsite Principal Engineer, HBM Memory Subsystem Architect

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About the role

  • Memory Subsystem Architect responsible for developing innovative HBM DRAM products at Micron. Collaborating with cross-functional teams to drive next-generation memory architectures and performance improvements.

Responsibilities

  • Develop innovative memory subsystem architectures for HBM-based AI/ML solutions
  • Define Memory and RAS architecture requirements and drive end‑to‑end architectural specification for next‑generation memory subsystems
  • Collaborate with internal and external partners to develop novel architectures and detailed IP requirements across all memory subsystem components
  • Lead engagement with IP vendors, including evaluation and selection of interface IP and functional IP blocks
  • Analyze benchmarks, workloads, and simulation results to identify performance and efficiency innovation opportunities in memory subsystems
  • Partner with RTL, validation, and multi-functional teams to ensure successful and timely implementation of subsystem features

Requirements

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
  • Minimum of 10 years of experience in memory subsystem architecture and design
  • Deep understanding of memory controller design and memory types (DDR, LPDDR, GDDR, HBM)
  • Experience with PHY design and understanding of signal integrity issues
  • Proficiency in Network-on-Chip (NoC) architecture and design
  • Familiarity with industry-standard bus protocols such as AXI, AMBA, AHB, DFI, HIF, etc

Benefits

  • Health insurance
  • 401(k) matching
  • Paid time off
  • Paid family leave
  • Robust paid time-off program
  • Flexible working hours

Job title

Principal Engineer, HBM Memory Subsystem Architect

Job type

Experience level

Lead

Salary

$162,000 - $344,000 per year

Degree requirement

Bachelor's Degree

Location requirements

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