Senior SoC Design Verification Engineer at Altera handling architecture verification tasks. Collaborating with teams to ensure full coverage verification planning and execution.
About the role
- SoC Design Verification Lead responsible for leading SoC architecture verification and coordination with design, SW, and architecture teams. Overseeing full chip and system functional verification according to specifications.
Responsibilities
- Lead pre-silicon verification strategy and execution for SoC verification
- Performs functional logic verification at multiple levels ( block, subsystem and full chip )
- Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications
- Documents, reviews, and executes the verification strategy plan on different methodologies/techniques (e.g., gate-level-simulation strategy, power patterns/aware simulations) used to enable feature coverage as per the microarchitecture specifications
- Executes verification plans and defines and runs system simulation models to verify the FPGA design, analyze power and timing, and uncover bugs
- Replicates, root causes, and debugs post-si issues in the pre-silicon environment
- Absorbs learning from post-silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages, and proliferates to future products
- Complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure)
Requirements
- B.Tech/M.Tech in Electrical Engineering, Electronics, or related field
- 12+ years of experience
- Familiar with System Verilog language
- Experience on UVM verification methodology, and formal verification method
- Working knowledge of scripting in Linux/ Unix environments as well as proficiency in Perl and or Python is desirable
- Experience with ARM based SoC verification
- Experience with protocols such as PCIe, Ethernet, USB, TSN, etc
- Experience with Design for Debug (JTAG, High speed USB, PCIe based debug will be an add on
Benefits
- Health insurance
- Retirement plans
- Paid time off
- Professional development opportunities
Job title
Job type
Experience level
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Not specified
Degree requirement
Tech skills
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