CPU verification engineer at Intel developing validation strategies for CPU logic designs. Collaborating with architects and designers to ensure rigorous pre-silicon verification methodologies.
Responsibilities
Develop and execute comprehensive verification plans to validate CPU logic against architectural specifications
Build scalable UVM-based testbenches and define robust functional coverage models
Run system-level simulations to uncover design bugs and ensure functional integrity
Debug and root-cause issues in the pre-silicon environment; implement corrective actions to resolve test failures
Collaborate closely with CPU architect and RTL designers to verify complex architectural and microarchitectural features
Document verification strategies and lead technical reviews with design and architecture teams
Maintain and enhance existing verification infrastructure and methodologies
Contribute to the definition and refinement of CPU architecture and microarchitecture features
Requirements
Bachelor's Degree in Electrical Electronics Engineering, Computer Engineering or in a STEM related field of study with 1+ years of relevant experience
Master’s Degree in Electrical Electronics Engineering, Computer Engineering or in a STEM related field of study 1+ years of experience developing SystemVerilog in UVM-based test-benches for reusable and scalable verification environments.
1+ years of experience in scripting language i.e. Python or Perl and C++
PhD in Electrical Electronics Engineering, Computer Engineering or in a STEM related field of study with 2+ years of industry experience (Preferred)
Understanding of digital logic design, including instruction set execution, ALUs, control units, registers, memory, and system buses (Preferred)
Knowledge and experience with x86 preferred, strong ASM skills a bonus (Preferred)
Familiarity with version control software (GIT) (Preferred)
Experience with Synopsys simulators (Preferred)
Excellent analytical and debugging skills, with a creative approach to problem-solving (Preferred)
Experience implementing validation strategies based on architectural and design feature changes (Preferred)
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