Senior TD Memory Quality and Reliability Engineer at Intel focusing on memory arrays and IP reliability. Leading technical efforts and providing expertise across various areas of responsibility.
Responsibilities
Lead technology Vccmin and/or fuse certification efforts to meet the needs of internal and foundry customers.
Investigate and understand reliability failure mechanisms and the underlying physics.
Analyze test chip Vccmin and/or fuse data to identify trends and potential issues, providing feedback to the process on conversion decisions and driving processes to meet certification requirements.
Characterize SRAM memory bit cell margin and noise; perform Sil2Sim for product design guidance.
Characterize fuse programming and read margin.
Develop and enhance statistical modeling methods for Vccmin reliability.
Engage and lead effort in Cert method definition/update for Vccmin/fuse.
Collaborate with cross-functional teams to ensure quality and reliability standards are met throughout the product lifecycle.
Communicate project status, technical findings, and recommendations to stakeholders, including process/LYA, device, design, and customers.
Drive continuous improvement initiatives to enhance quality and reliability processes and methodologies.
Provide technical leadership and mentorship to junior engineers and team members.
Requirements
Ph.D. in Electrical Engineering, Material Science, Physics, or related field, with 3+ years of relevant experience in semiconductor device physics and data analysis.
Masters in Electrical Engineering, Material Science, Physics, or a related field, with 6+ years of relevant experience in semiconductor device physics and data analysis.
Proficient in using JMP.
Demonstrated knowledge of memory array design and testing.
Experience in quality and reliability methods and modeling.
Proficiency in scripting languages such as Python or JSL (preferred).
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