Hybrid Physical Design Staff Engineer

at Factorial

• Job title: Physical Design Staff Engineer
• Job type: Full Time
• Experience level: Lead
• Salary: Not specified
• Degree requirement: Bachelor's Degree
• Tech skills: Perl, Python
• Location requirements: Hybrid, Roma, Italy

About the role

• Physical Design Staff Engineer ensuring functional design intent during physical implementation at Openchip. Collaborating with top-tier partners across Europe in a hybrid environment.

Responsibilities

• Drive the entire implementation flow (Floorplanning, P&R, Clock Tree Synthesis) with a 'constraint-driven' approach.
• Functional Context Analysis: Anticipate routing and timing bottlenecks.
• Dynamic Constraint Management: Analyze, clean, and regenerate timing constraints at every stage (Pre-Placement, Placement, Pre-CTS, Post-CTS, Sign-off), ensuring they reflect both the physical reality of the silicon and the functional requirements (e.g., Multi-Cycle Paths, distinguishing real vs. spurious False Paths).
• Manage complex timing closures (Multi-clock domains, asynchronous interfaces) using advanced techniques (DMSA, OCV/AOCV/POCV).
• Drive ECO (Engineering Change Order) strategies not just at the gate level, but by proposing changes when the physical impact requires it.
• Oversee Signal Integrity (SI) and Power Integrity analysis.

Requirements

• Experience: 10+ years in the semiconductor industry with a focus on Physical Design and Digital Implementation.
• Constraint Mastery: Expert knowledge of the SDC format and the ability to write and debug complex constraints for multi-mode/multi-corner (MMMC) designs.
• Timing Closure: Solid experience in STA (PrimeTime/Tempus), CDC (Clock Domain Crossing) analysis, and managing hold/setup violations in advanced technology nodes or critical automotive contexts.
• Scripting: Excellent automation skills (Tcl, Python, Perl) for report analysis and massive data flow management.

Benefits

• Join a highly innovative microelectronics company working at the forefront of RISC-V and advanced SoC technologies.
• Opportunity to play a key technical leadership role bridging industry and public research.
• Collaboration with top-tier research institutions and industrial partners across Europe.
• Flexible working conditions and hybrid work environment.
• Competitive remuneration aligned with seniority and expertise.