Senior Design Verification Engineer working with a team on mixed-signal IC developments. Collaborating with top engineers on verification methodology improvements in a thriving workplace.
Responsibilities
Join silicon design verification team and work closely with digital/analog designers, applications engineers, and manufacturing test.
Participate in all aspects of verification for complete mixed-signal IC developments.
Work on complex verification systems and contribute to improvements in verification methodology.
Requirements
MS or PhD in Electrical Engineering or Computer Engineering.
Strong background with HDLs (e.g. Verilog, VHDL) and HVLs (e.g. SystemVerilog/UVM, OVM, AVM, Vera).
At least 5+ years of experience in silicon design or verification.
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