Staff PDK Engineer assisting in the design of high-performance mixed-signal ASICs at Cirrus Logic. Collaborating on PDK development and EDA methodology.
Responsibilities
Assist in designing high-performance mixed-signal ASICs by developing & integrating technology files, models & decks (DRC, LVS, and PEX) to support our PDKs.
Collaborate closely with design teams, foundries, and our silicon technology team to develop and verify PDKs.
Apply expertise to EDA methodology, including development, qualification, automation, and support, as well as evaluation & development of new tools & flows.
Work closely with design & layout teams to support tape out of IC designs.
Develop and qualify physical verification decks.
Install, customize and test foundry PDKs.
Customize and test our analog/mixed-signal environment.
Support IC tape out methodology.
Mentor other PDK Engineers.
Requirements
BS in Electrical or Computer Engineering and 12+ years of proven experience in related CAD field or MS in Electrical or Computer Engineering and 10+ years of exp.
A strong understanding of front-to-back analog/mixed-signal design methodology.
Strong experience on DRC, LVS and parasitic extraction flow (based on Calibre is a plus).
Experience with PDK installation, customization and QA.
Experience with PDK development and validation.
Ability to effectively support layout & design teams.
Able to demonstrate programming knowledge in Perl, SKILL, Tcl, Python and/or shell scripting.
A hardworking individual who possesses strong organizational & interpersonal skills, and demonstrates versatility in handling a wide range of CAD methodology issues.
Expertise in one or more of the following areas: Developing Cadence dfII technology files, netlisting, simulation & Pcells OR Development of physical verification decks in Calibre DRC.
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