Design Internship at our Milan Office specializing in Fashion and Knitwear. Supporting design development and research in a dynamic studio environment.
About the role
- Design Verification Engineer responsible for architecting verification environments for ASIC SoC at a leading technology company. Involves defining verification plans and developing complex test benches.
Responsibilities
- Responsible for architecting Verification Environment for ASIC SoC and providing verification support from defining verification plan to multi-million gate product tapeout & for Test design and development
- Develop complex self checking test benches with constraint random stimulus generation.
- Architect SoC test FW and create test plan documentation to cover ASIC features.
- Develop and debug SoC ASIC platform test FW and specific tests in C/C++.
- Partner in methodology development activities & actively planning, analyzing and reviewing functional and technical specification documents
- Implement and maintain integrated end-to-end formal verification flow for the formal verification objective.
- Develop/modify scripts to automate the verification process.
- Develop verification environment including environment assumptions, assertions, and cover properties in context of the verification plan.
Requirements
- Typically requires a minimum of 8 years of related experience with a 4 year degree; or 6 years and an advanced degree; or equivalent experience.
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