IP Systems Engineer driving and executing the functional test plan for virtualization IPs at AMD. Engaging in technical innovation and collaborative efforts to enhance AMD’s validation capabilities.
Responsibilities
Defining and executing the overall functional test plan and verification strategy for virtualization IPs
Driving technical innovation to enhance AMD’s capabilities in validation/verification, including tool and script development, technical and procedural methodology enhancement, and various internal and cross-functional technical initiatives.
Debug of issues found during pre-silicon, bringup, validation, and production phases of SOC programs
Working closely with supporting teams in design, diagnostics, emulation, firmware, and driver to ensure readiness for first silicon arrival, enablement of functionality, and debug of critical features.
Engaging on pre-silicon verification efforts, including but not limited to FPGA-based emulation, Design Verification (DV), and other software/hardware modeling frameworks.
Leading collaborative technical discussions to drive resolution on technical issues and roll out technical initiatives
Developing knowledge of system architecture/debug and other IP’s
Supporting issues on customer platforms as requested by customer support teams
Requirements
Experience with board/platform-level debug, including clock/power delivery, sequencing, analysis, and optimization
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